1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly, to a semiconductor memory having a test circuit for parallelly testing a plurality of memory cells.
2. Description of the Related Art
There has been proposed a test mode for testing in parallel a plurality of memory cells of a semiconductor memory in a way that shortens the time required for the test (M. Kumanoya et al., ISSCC85 Dig. of Tech. papers, pp. 240-241).
FIG. 15A is a plan view showing a typical layout of a conventional dynamic random access memory (DRAM) having the above type of test mode. FIG. 15B is an enlarged plan view of the part Z in FIG. 15A.
Referring to FIGS. 15A and 15B, this DRAM comprises four memory arrays 31 located in the four corners of a memory chip, a row decoder 32 and a column decoder 33 furnished to each of the memory arrays 31, and a peripheral circuit region 34 provided in the middle of the memory chip. Each memory array 31 includes a plurality of subarrays 35 and of sense amplifier zones 36.
Each subarray 35 comprises a plurality of memory cells MC arranged in the directions of rows and columns, a word line WL furnished to correspond with each memory cell row, and a bit line pair BL, /BL provided to correspond with each memory cell column.
Each sense amplifier zone 36 includes a sense amplifier and a column selection gate CGS furnished to correspond with each column, and four signal input/output line pairs I/O1-I/O4. Each column selection gate CGS is composed of two N-channel MOS transistors.
The bit line pairs BL, /BL; sense amplifiers SA, and column selection gates CGS are arranged beforehand in groups of four each. The bit line pairs BL1,/BL1; . . . ; BL4, /BL4 of each group are connected to the signal input/output line pairs I/O1-I/O4 respectively via the corresponding sense amplifiers SA1-SA4 and column selection gates CGS1-CGS4.
Each group is provided with a single column selection line CSL. When the column decoder 33 selects the column selection line CSL of a particular group, the column selection gates CGS1-CGS4 connected to that column selection line CSL conduct. This causes the bit line pairs BL1, /BL1; . . . ; BL4, /BL4 of the group to be connected respectively to the signal input/output line pairs I/O1-I/O4. The column selection line CSL is furnished in common with the multiple subarrays 35 and sense amplifier zones 36.
As shown in FIG. 16, the peripheral circuit region 34 includes a data input terminal Din, a write buffer 37, four write data buses WBP1-WBP4, and a write driver 38. The write buffer 37 receives write data from the outside via the data input terminal Din, and places the received data onto the write data buses WBP1-WBP4 leading to the object of access. The write driver 38 amplifies the data over the write data buses WBP1-WBP4, and feeds the amplified data to the corresponding signal input/output line pairs I/O1-I/O4.
The peripheral circuit region 34 further comprises a preamplifier 39, four read data buses RB1-RB4, a multiplexer 40, a coincidence detection circuit (exclusive-OR gate) 41, and a data output terminal Dout. The preamplifier 39 amplifies the data over the signal input/output line pairs I/O1-I/O4, and forwards the amplified data to the corresponding read data buses RB1-RB4. The multiplexer 40 outputs, in a read operation, the data of the read data buses RB1-RB4 serially to the data output terminal Dout. The coincidence detection circuit 41, in a test mode, checks to see if the data over the read data buses RB1-RB4 coincide with one another. In case of coincidence, the coincidence detection circuit 41 outputs to the data output terminal Dout a high-level pass flag indicating that the memory cells MC under test are normal.
Below is a description of how the DRAM outlined above with reference to FIGS. 15A, 15B and 16 works. In a normal write operation, data is input serially through the data input terminal Din. The input data is transferred by the write buffer 37 to the write data buses WBP1-WBP4 leading to the object of access. The transferred data is amplified by the write driver 38 before being input to the corresponding signal input/output line pairs I/O1-I/O4. The data over the signal input/output line pairs I/O1-I/O4 is fed to the four bit line pairs BL1, /BL1; . . . ; BL4, /BL4 of the group selected by the column decoder 33. From there, the data is written simultaneously to the four memory cells MC connected to the word line WL selected by the row decoder 30.
In a normal read operation, the multiplexer 40 is activated and the coincidence detection circuit 41 inactivated. The relevant bit line pairs BL, /BL are fed with the data read from the memory cells MC connected to the word line WL selected by the row decoder 32. The signal input/output line pairs I/O1-I/O4 are then supplied with the data from the four bit line pairs BL1, /BL1; . . . ; BL4, /BL4 of the group selected by the column decoder 33. The preamplifier 39 amplifies the data over the signal input/output line pairs I/O1-I/O4 and forwards the amplified data to the corresponding read data buses RB1-RB4. From there, the data is output serially by the multiplexer 40 to the data output terminal Dout.
In a write operation where the test mode is in effect, a data item entered through the data input terminal Din is transferred by the write buffer 37 onto four write data buses WBP1-WBP4. Thereafter, the data is written to four memory cells MC under test as in the case of the normal write operation. That is, in the test mode, the same data is written simultaneously to four memory cells MC.
The writing of data to the four memory cells MC is followed by the input, via the data input terminal Din, illustratively of the data item complementary to the previously entered data. The adjacent word line WL is then selected and the same write operation is carried out. It follows that, as shown in FIG. 17, data is written inverted to every four memory cells MC of the same row and to every memory cell MC of the same column.
In a read operation where the test mode is in effect, the multiplexer 40 is inactivated and the coincidence detection circuit 41 activated. The relevant bit line pairs BL, /BL are fed with the data read from the memory cells MC connected to the word line WL selected by the row decoder 32. The signal input/output line pairs I/O1-1/O4 are then supplied with the data from the four bit line pairs BL1, /BL1; . . . ; BL4, /BL4 of the group selected by the column decoder 33. The preamplifier 39 amplifies the data over the signal input/output line pairs I/O1-1/O4 and forwards the amplified data to the corresponding read data buses RB1-RB4. Upon detecting coincidence between the data on the read data buses RB1-RB4, the coincidence detection circuit 41 outputs a high-level pass flag indicating that the four memory cells MC under test are normal. In case of a mismatch between the data on the read data buses RB1-RB4, the coincidence detection circuit 41 outputs a low-level fail flag indicating that at least one of the four memory cells MC in question is defective. After this, the adjacent word line WL is illustratively selected and the same read operation is repeated.
In the test mode, this DRAM allows its memory cells MC to be tested four at a time in parallel. This means that the above-described DRAM can be tested four times as fast as DRAM's wherein the memory cells MC are tested one by one. This scheme results in appreciable savings in testing time and in the cost required of the tests.
However, the above conventional scheme has the following disadvantage: in the above test mode, the same data item is written to every four memory cells MC (e.g., those indicated by solid circles in FIG. 15B). As a result, where different data items are written to two contiguous memory cells MC, the conventional setup has a reduced capability of detecting a faulty memory caused by the interference between the memory cells.